The present invention relates to a data processing device, and is particularly suited to a data processing device including a plurality of CPUs (Central Processing Units) of an SIMD (Single Instruction Multiple Data) type.
Nowadays, there are increasing demands for high processing performance on media processing (image processing, speech processing). The media processing is characterized by performing the same calculation on a plurality of media data streams (images, speech). By parallelly performing such processing, it is possible to improve the processing performance. Nowadays, as processing devices for parallelly performing media processing, multi-core CPUs, SIMD-type media processors, dedicated media engines, and the like are developed and included in various products. The SIMD is architecture of data processing devices comprised of multi-core CPUs or the like for implementing processing for parallelly performing the same calculation on a plurality of data streams, and is therefore suitable for media processing including image processing and speech processing which perform the same calculation on a plurality of media data streams (pixels, sounds).
In the multi-core CPU, a plurality of CPUs parallelly perform different media processes. In this case, each CPU has an instruction cache memory, and can fetch an instruction simultaneously and independently. On the other hand, the SIMD-type media processor and the dedicated media engine are of architecture specific to media processing. In general, a system configured with the SIMD-type media processor or the dedicated media engine also includes CPUs for executing processing other than media processing.
Japanese Unexamined Patent Publication No. Hei 9(1997)-198310 (Patent Document 1) discloses a multiprocessor system in which a plurality of units each comprised of a processor, a cache memory, and a control section are coupled to a main storage device through a common bus, and the control sections of the units are coupled to each other through a dedicated bus. When a cache miss occurs in one unit, address information at this time is transferred to another unit through the dedicated bus, and the cache memory is accessed based on the address received by the unit. After a hit, read data is supplied through the dedicated bus to the unit where the cache miss has occurred.
Japanese Unexamined Patent Publication No. Hei 4(1992)-291642 (Patent Document 2) discloses a multiprocessor system in which a plurality of processors each provided with a dedicated cache memory are coupled to a main storage device through a common bus. If target data exists in one cache memory, the data is read from the cache memory. If target data does not exist in one cache memory and exists in another cache memory, the data is read from the cache memory where the data exists, and is transferred to a processor that has requested the data.